i2c-thermo-verilog-xdc の変更点

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---

[[I2Cデバイスを手で動かしてみる]]

* Vivado または ISEで以下の verilog を入力 [#p3bd8c82]
- verilog 
-- top.v
 module top(sSegAnode, sSegCathode, sw, led, cled1, cled2, 
                    bu, bd, bl, br, bc, scl, sda, bclck );
   output [7:0] sSegAnode;
   output [7:0] sSegCathode;
   output [15:0] led;     // led[8] ... if sda is sending, corresponding to the last sended sda, else corresponding to the last received sda
                         //               it is shifted to left when a positive edge of scl is detected.
 		         //  led[0] corresponding to sw[0]
 		         //  led[1] corresponding to sw[1]
 			 //  led[2] corresponsing to center button, bc.
   output [2:0] cled1, cled2;
   input [15:0] sw;       // sw[15:8] ... for setting sda send data, sw[7:0] ... for controlling
                         //    sw[0] ... if 1 sda is high=Z=high impedance, else low;
             												  
   input bu, bd, bl, br, bc, bclck;    //  bd corresponding to !reset.
                         //  bc corresponding to scl.  scl=sw[0]|bc
 			 //  if posedge bl is detected, sw is shown in hex in the 7seg led array.
   
   inout scl, sda;
   wire BNx, BWx, BEx, BCx;
   wire [7:0] swx;
   wire reset;
   wire sclRw, sdaRw; // write=1, read=0;
   reg [7:0] data;
   assign led[15:8]=data;
   assign led[7:0]=swx;
   assign reset=~bd;
   assign scl=BCx?1'bz:1'b0;
   assign cled1[2]=scl;
   assign sda=(swx[0])?1'bz:1'b0;
   assign cled2[2]=sda;
   always @(posedge scl, negedge reset) begin
     if(!reset) data<=0;
 	 else
     data<={data[6:0],sda};
   end
     
   chattering #(12) chattering0(.clk(bclck), .reset(reset), 
              .in({bu,bl,br,bc,sw[7:0]}), .out({BNx,  BWx, BEx, BCx,swx}));
 //  assign BNx=BN;
 //  assign BWx=BW;
 //  assign BEx=BE;
 //  assign BCx=BC;
   sSegArray sSegArray0(.clk(bclck), .reset(reset), 
             .load(1), .d({data,swx}), .anode(sSegAnode), .cathode(sSegCathode));
   
 endmodule

-- chattering.v
 module chattering(clk, reset, in, out
 );
 parameter N=1;
 input clk, reset;
 input [N-1:0]in;
 output [N-1:0]out;
 reg [N-1:0]out;
 reg [21:0] count;
 
 always @(posedge clk or negedge reset)
 if(!reset) count <=0;
 else count <= count +1;
 
 always @(posedge clk)
 if(count==0) out <= in;
 
 endmodule
-- sSegArray.v
 module sSegArray(
     clk,reset,load,d, 
 	 anode, cathode
     ); 
 parameter N=32;
 input clk,reset,load;
 input [N-1:0] d; 
 output [7:0] anode;
 output [7:0] cathode;
 reg [7:0] anode;
 reg [7:0] cathode;
 reg [31:0] q;
 
 wire [2:0] selectedSeg;
 wire [7:0] wOneSeg;
 reg segClk;
 
 counter #(8) waitOneSeg(.clk(clk), .reset(reset), .load(0), .inc(1), .d(16'h0000), .q(wOneSeg));
 
 //assign segClk= (wOneSeg==0)? ~segClk: segClk;
 always @(posedge clk, negedge reset) begin
   if(!reset) segClk<=0;
   else
   if (wOneSeg==0) segClk<=~segClk; 
 end
 
 counter #(3) selector(.clk(segClk),.reset(reset),.load(0), .inc(1), .d(4'h0), .q(selectedSeg));
 //counter #(3) selector(.clk(clk), .reset(reset), .load(0), .inc(1), .d(4'h0), .q(selectedSeg));
  
 always @(posedge clk, negedge reset)
 begin
   if(!reset) anode=8'hFE;   // note!  anode is connected by pnp transistor.  
   else                      // in order to active one 7seg, low should be setted to the 7seg. 
    case (selectedSeg)
 	   3'b000: anode=8'hFE;
 		3'b001: anode=8'hFD;
 		3'b010: anode=8'hFB;
 		3'b011: anode=8'hF7;
 		3'b100: anode=8'hEF;
 		3'b101: anode=8'hDF;
 		3'b110: anode=8'hBF;
 		3'b111: anode=8'h7F;
 	endcase
 end
 
 reg [3:0] selectedVal;
 
 always @(posedge clk, negedge reset)
 begin
   if(!reset) cathode=8'h03;                   // note! when one segment of the cathode is low,
   else                                        //  and its anode is low, the segment glow.
   case (selectedVal)                         //          ca
     4'b0000: cathode=8'h03;   //8'hfc; 0              ------
     4'b0001: cathode=8'h9f;   //8'h60; 1              /     /
     4'b0010: cathode=8'h25;   //8'hda; 2              /cf   / cb 
     4'b0011: cathode=8'h0d;   //8'hf2; 3              /     /
     4'b0100: cathode=8'h99;   //8'h66; 4               -----
     4'b0101: cathode=8'h49;   //8'hb6; 5              /  cg  /
     4'b0110: cathode=8'h41;   //8'hbe; 6              /ce    / cc
     4'b0111: cathode=8'h1f;   //8'he0; 7              /      /
     4'b1000: cathode=8'h01;   //8'hfe; 8               ------     . ch
     4'b1001: cathode=8'h09;   //8'hf6; 9                  cd
     4'b1010: cathode=8'h11;   //8'hee; A
     4'b1011: cathode=8'hc1;   //8'h3e; B
     4'b1100: cathode=8'h63;   //8'h9c; C
     4'b1101: cathode=8'h85;   //8'h7c; D
     4'b1110: cathode=8'h61;   //8'h9e; E
     4'b1111: cathode=8'h71;   //8'h8e; F
    endcase
 end
 
 always @(posedge clk, negedge reset)
 begin
   if(!reset) selectedVal=q[3:0];
   else
    case (selectedSeg)
 	  3'b000: selectedVal=q[3:0];
 	  3'b001: selectedVal=q[7:4];
 	  3'b010: selectedVal=q[11:8];
 	  3'b011: selectedVal=q[15:12];
 	  3'b100: selectedVal=q[19:16];
 	  3'b101: selectedVal=q[23:20];
 	  3'b110: selectedVal=q[27:24];
 	  3'b111: selectedVal=q[31:28];
 	endcase
 end
 
 always @(posedge clk, negedge reset)
 begin
   if(!reset) q=0;
   else
   if(load) q=d;
 end
 
 endmodule
-- counter.v
 module counter(clk, reset, load, inc, d, q );
 parameter N=16;
 
 input clk, reset, load, inc;
 input [N-1:0] d; 
 output [N-1:0] q;
 reg [N-1:0] q;
 
 always @(posedge clk or negedge reset)
 if(!reset) q <=0;
 else if(load) q<=d; 
 else if(inc) q<=q+1;
 endmodule
-- top.xdc (Vivadoの場合)
 ## Clock signal
 ##Bank = 35, Pin name = IO_L12P_T1_MRCC_35,					Sch name = CLK100MHZ
 set_property PACKAGE_PIN E3 [get_ports bclck]	
 	set_property IOSTANDARD LVCMOS33 [get_ports bclck]
 #	create_clock -add -name sys_clk_pin  -period 10.00 -waveform {0 5} [get_ports bclk]
  
 ## Switches
 ##Bank = 34, Pin name = IO_L21P_T3_DQS_34,					Sch name = SW0
 set_property PACKAGE_PIN U9 [get_ports {sw[0]}]					
 	set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
 ##Bank = 34, Pin name = IO_25_34,							Sch name = SW1
 set_property PACKAGE_PIN U8 [get_ports {sw[1]}]					
 	set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
 ##Bank = 34, Pin name = IO_L23P_T3_34,						Sch name = SW2
 set_property PACKAGE_PIN R7 [get_ports {sw[2]}]					
 	set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
 ##Bank = 34, Pin name = IO_L19P_T3_34,						Sch name = SW3
 set_property PACKAGE_PIN R6 [get_ports {sw[3]}]					
 	set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
 ##Bank = 34, Pin name = IO_L19N_T3_VREF_34,					Sch name = SW4
 set_property PACKAGE_PIN R5 [get_ports {sw[4]}]					
 	set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}]
 ##Bank = 34, Pin name = IO_L20P_T3_34,						Sch name = SW5
 set_property PACKAGE_PIN V7 [get_ports {sw[5]}]					
 	set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}]
 ##Bank = 34, Pin name = IO_L20N_T3_34,						Sch name = SW6
 set_property PACKAGE_PIN V6 [get_ports {sw[6]}]					
 	set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]
 ##Bank = 34, Pin name = IO_L10P_T1_34,						Sch name = SW7
 set_property PACKAGE_PIN V5 [get_ports {sw[7]}]					
 	set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]
 ##Bank = 34, Pin name = IO_L8P_T1-34,						Sch name = SW8
 set_property PACKAGE_PIN U4 [get_ports {sw[8]}]					
 	set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]
 ##Bank = 34, Pin name = IO_L9N_T1_DQS_34,					Sch name = SW9
 set_property PACKAGE_PIN V2 [get_ports {sw[9]}]					
 	set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}]
 ##Bank = 34, Pin name = IO_L9P_T1_DQS_34,					Sch name = SW10
 set_property PACKAGE_PIN U2 [get_ports {sw[10]}]					
 	set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}]
 ##Bank = 34, Pin name = IO_L11N_T1_MRCC_34,					Sch name = SW11
 set_property PACKAGE_PIN T3 [get_ports {sw[11]}]					
 	set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}]
 ##Bank = 34, Pin name = IO_L17N_T2_34,						Sch name = SW12
 set_property PACKAGE_PIN T1 [get_ports {sw[12]}]					
 	set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}]
 ##Bank = 34, Pin name = IO_L11P_T1_SRCC_34,					Sch name = SW13
 set_property PACKAGE_PIN R3 [get_ports {sw[13]}]					
 	set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}]
 ##Bank = 34, Pin name = IO_L14N_T2_SRCC_34,					Sch name = SW14
 set_property PACKAGE_PIN P3 [get_ports {sw[14]}]					
 	set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}]
 ##Bank = 34, Pin name = IO_L14P_T2_SRCC_34,					Sch name = SW15
 set_property PACKAGE_PIN P4 [get_ports {sw[15]}]					
 	set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}]
 
 ## LEDs
 ##Bank = 34, Pin name = IO_L24N_T3_34,						Sch name = LED0
 set_property PACKAGE_PIN T8 [get_ports {led[0]}]					
 	set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
 ##Bank = 34, Pin name = IO_L21N_T3_DQS_34,					Sch name = LED1
 set_property PACKAGE_PIN V9 [get_ports {led[1]}]					
 	set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
 ##Bank = 34, Pin name = IO_L24P_T3_34,						Sch name = LED2
 set_property PACKAGE_PIN R8 [get_ports {led[2]}]					
 	set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
 ##Bank = 34, Pin name = IO_L23N_T3_34,						Sch name = LED3
 set_property PACKAGE_PIN T6 [get_ports {led[3]}]					
 	set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
 ##Bank = 34, Pin name = IO_L12P_T1_MRCC_34,					Sch name = LED4
 set_property PACKAGE_PIN T5 [get_ports {led[4]}]					
 	set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
 ##Bank = 34, Pin name = IO_L12N_T1_MRCC_34,					Sch	name = LED5
 set_property PACKAGE_PIN T4 [get_ports {led[5]}]					
 	set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
 ##Bank = 34, Pin name = IO_L22P_T3_34,						Sch name = LED6
 set_property PACKAGE_PIN U7 [get_ports {led[6]}]					
 	set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
 ##Bank = 34, Pin name = IO_L22N_T3_34,						Sch name = LED7
 set_property PACKAGE_PIN U6 [get_ports {led[7]}]					
 	set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
 ##Bank = 34, Pin name = IO_L10N_T1_34,						Sch name = LED8
 set_property PACKAGE_PIN V4 [get_ports {led[8]}]					
 	set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
 ##Bank = 34, Pin name = IO_L8N_T1_34,						Sch name = LED9
 set_property PACKAGE_PIN U3 [get_ports {led[9]}]					
 	set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
 ##Bank = 34, Pin name = IO_L7N_T1_34,						Sch name = LED10
 set_property PACKAGE_PIN V1 [get_ports {led[10]}]					
 	set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
 ##Bank = 34, Pin name = IO_L17P_T2_34,						Sch name = LED11
 set_property PACKAGE_PIN R1 [get_ports {led[11]}]					
 	set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
 ##Bank = 34, Pin name = IO_L13N_T2_MRCC_34,					Sch name = LED12
 set_property PACKAGE_PIN P5 [get_ports {led[12]}]					
 	set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}]
 ##Bank = 34, Pin name = IO_L7P_T1_34,						Sch name = LED13
 set_property PACKAGE_PIN U1 [get_ports {led[13]}]					
 	set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}]
 ##Bank = 34, Pin name = IO_L15N_T2_DQS_34,					Sch name = LED14
 set_property PACKAGE_PIN R2 [get_ports {led[14]}]					
 	set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}]
 ##Bank = 34, Pin name = IO_L15P_T2_DQS_34,					Sch name = LED15
 set_property PACKAGE_PIN P2 [get_ports {led[15]}]					
 	set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]
 
 ##Bank = 34, Pin name = IO_L5P_T0_34,						Sch name = LED16_R
 set_property PACKAGE_PIN K5 [get_ports {cled1[2]}]					
 	set_property IOSTANDARD LVCMOS33 [get_ports {cled1[2]}]
 ##Bank = 15, Pin name = IO_L5P_T0_AD9P_15,					Sch name = LED16_G
 set_property PACKAGE_PIN F13 [get_ports {cled1[1]}]				
	set_property IOSTANDARD LVCMOS33 [get_ports {cled1[1]}]
 ##Bank = 35, Pin name = IO_L19N_T3_VREF_35,					Sch name = LED16_B
 set_property PACKAGE_PIN F6 [get_ports {cled1[0]}]					
 	set_property IOSTANDARD LVCMOS33 [get_ports {cled1[0]}]
 ##Bank = 34, Pin name = IO_0_34,								Sch name = LED17_R
 set_property PACKAGE_PIN K6 [get_ports {cled2[2]}]					
 	set_property IOSTANDARD LVCMOS33 [get_ports {cled2[2]}]
 ##Bank = 35, Pin name = IO_24P_T3_35,						Sch name =  LED17_G
 set_property PACKAGE_PIN H6 [get_ports {cled2[1]}]					
 	set_property IOSTANDARD LVCMOS33 [get_ports {cled2[1]}]
 ##Bank = CONFIG, Pin name = IO_L3N_T0_DQS_EMCCLK_14,			Sch name = LED17_B
 set_property PACKAGE_PIN L16 [get_ports {cled2[0]}]					
 	set_property IOSTANDARD LVCMOS33 [get_ports {cled2[0]}]
 
 ##7 segment display
 ##Bank = 34, Pin name = IO_L2N_T0_34,						Sch name = CA
 set_property PACKAGE_PIN L3 [get_ports {sSegCathode[7]}]					
	set_property IOSTANDARD LVCMOS33 [get_ports {sSegCathode[7]}]
 ##Bank = 34, Pin name = IO_L3N_T0_DQS_34,					Sch name = CB
 set_property PACKAGE_PIN N1 [get_ports {sSegCathode[6]}]					
 	set_property IOSTANDARD LVCMOS33 [get_ports {sSegCathode[6]}]
 ##Bank = 34, Pin name = IO_L6N_T0_VREF_34,					Sch name = CC
 set_property PACKAGE_PIN L5 [get_ports {sSegCathode[5]}]					
 	set_property IOSTANDARD LVCMOS33 [get_ports {sSegCathode[5]}]
 ##Bank = 34, Pin name = IO_L5N_T0_34,						Sch name = CD
 set_property PACKAGE_PIN L4 [get_ports {sSegCathode[4]}]					
 	set_property IOSTANDARD LVCMOS33 [get_ports {sSegCathode[4]}]
 ##Bank = 34, Pin name = IO_L2P_T0_34,						Sch name = CE
 set_property PACKAGE_PIN K3 [get_ports {sSegCathode[3]}]					
 	set_property IOSTANDARD LVCMOS33 [get_ports {sSegCathode[3]}]
 ##Bank = 34, Pin name = IO_L4N_T0_34,						Sch name = CF
 set_property PACKAGE_PIN M2 [get_ports {sSegCathode[2]}]					
 	set_property IOSTANDARD LVCMOS33 [get_ports {sSegCathode[2]}]
 ##Bank = 34, Pin name = IO_L6P_T0_34,						Sch name = CG
 set_property PACKAGE_PIN L6 [get_ports {sSegCathode[1]}]					
 	set_property IOSTANDARD LVCMOS33 [get_ports {sSegCathode[1]}]
 
 ##Bank = 34, Pin name = IO_L16P_T2_34,						Sch name = DP
 set_property PACKAGE_PIN M4 [get_ports sSegCathode[0]]							
 	set_property IOSTANDARD LVCMOS33 [get_ports sSegCathode[0]]
 
 
 ##Bank = 34, Pin name = IO_L18N_T2_34,						Sch name = AN0
 set_property PACKAGE_PIN N6 [get_ports {sSegAnode[0]}]					
 	set_property IOSTANDARD LVCMOS33 [get_ports {sSegAnode[0]}]
 ##Bank = 34, Pin name = IO_L18P_T2_34,						Sch name = AN1
 set_property PACKAGE_PIN M6 [get_ports {sSegAnode[1]}]					
 	set_property IOSTANDARD LVCMOS33 [get_ports {sSegAnode[1]}]
 ##Bank = 34, Pin name = IO_L4P_T0_34,						Sch name = AN2
 set_property PACKAGE_PIN M3 [get_ports {sSegAnode[2]}]					
 	set_property IOSTANDARD LVCMOS33 [get_ports {sSegAnode[2]}]
 ##Bank = 34, Pin name = IO_L13_T2_MRCC_34,					Sch name = AN3
 set_property PACKAGE_PIN N5 [get_ports {sSegAnode[3]}]					
 	set_property IOSTANDARD LVCMOS33 [get_ports {sSegAnode[3]}]
 ##Bank = 34, Pin name = IO_L3P_T0_DQS_34,					Sch name = AN4
 set_property PACKAGE_PIN N2 [get_ports {sSegAnode[4]}]					
 	set_property IOSTANDARD LVCMOS33 [get_ports {sSegAnode[4]}]
 ##Bank = 34, Pin name = IO_L16N_T2_34,						Sch name = AN5
 set_property PACKAGE_PIN N4 [get_ports {sSegAnode[5]}]					
 	set_property IOSTANDARD LVCMOS33 [get_ports {sSegAnode[5]}]
 ##Bank = 34, Pin name = IO_L1P_T0_34,						Sch name = AN6
 set_property PACKAGE_PIN L1 [get_ports {sSegAnode[6]}]					
 	set_property IOSTANDARD LVCMOS33 [get_ports {sSegAnode[6]}]
 ##Bank = 34, Pin name = IO_L1N_T034,							Sch name = AN7
 set_property PACKAGE_PIN M1 [get_ports {sSegAnode[7]}]					
 	set_property IOSTANDARD LVCMOS33 [get_ports {sSegAnode[7]}]
 
 ##Buttons
 ##Bank = 15, Pin name = IO_L3P_T0_DQS_AD1P_15,				Sch name = CPU_RESET
 #set_property PACKAGE_PIN C12 [get_ports btnCpuReset]				
 	#set_property IOSTANDARD LVCMOS33 [get_ports btnCpuReset]
 ##Bank = 15, Pin name = IO_L11N_T1_SRCC_15,					Sch name = BTNC
 set_property PACKAGE_PIN E16 [get_ports bc]						
 	set_property IOSTANDARD LVCMOS33 [get_ports bc]
 ##Bank = 15, Pin name = IO_L14P_T2_SRCC_15,					Sch name = BTNU
 set_property PACKAGE_PIN F15 [get_ports bu]						
 	set_property IOSTANDARD LVCMOS33 [get_ports bu]
 ##Bank = CONFIG, Pin name = IO_L15N_T2_DQS_DOUT_CSO_B_14,	Sch name = BTNL
 set_property PACKAGE_PIN T16 [get_ports bl]						
 	set_property IOSTANDARD LVCMOS33 [get_ports bl]
 ##Bank = 14, Pin name = IO_25_14,							Sch name = BTNR
 set_property PACKAGE_PIN R10 [get_ports br]						
 	set_property IOSTANDARD LVCMOS33 [get_ports br]
 ##Bank = 14, Pin name = IO_L21P_T3_DQS_14,					Sch name = BTND
 set_property PACKAGE_PIN V10 [get_ports bd]						
 	set_property IOSTANDARD LVCMOS33 [get_ports bd]
 
 ##Temperature Sensor
 ##Bank = 15, Pin name = IO_L14N_T2_SRCC_15,					Sch name = TMP_SCL
 set_property PACKAGE_PIN F16 [get_ports scl]					
 	set_property IOSTANDARD LVCMOS33 [get_ports scl]
 ##Bank = 15, Pin name = IO_L13N_T2_MRCC_15,					Sch name = TMP_SDA
 set_property PACKAGE_PIN G16 [get_ports sda]					
 	set_property IOSTANDARD LVCMOS33 [get_ports sda]
 ##Bank = 15, Pin name = IO_L1P_T0_AD0P_15,					Sch name = TMP_INT
 #set_property PACKAGE_PIN D14 [get_ports tmpInt]					
 	#set_property IOSTANDARD LVCMOS33 [get_ports tmpInt]
 ##Bank = 15, Pin name = IO_L1N_T0_AD0N_15,					Sch name = TMP_CT
 #set_property PACKAGE_PIN C14 [get_ports tmpCT]						
 	#set_property IOSTANDARD LVCMOS33 [get_ports tmpCT]
 
-- top.ucf (ISEの場合)
--- [[i2c-thermo-ise]]
----
#counter

       

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