operationMode | 機能 | Color LED 1 | cpuClk | cpuRun | cpuIn | sSegArray? | led | sclx, sdax | Color LED 2 | start |
0 | I2Cバスの手動操作 | {0,0,0} | BCx | 0 | 0 | {16{0}, data,swx[7:0]} | {data,swx[7:0]} | BCx,swx[0] | {0,sda,scl} | 0 |
1 | miniCPUの独立実行(手動クロック供給) | {0,0,1} | BCx | BNx | swx | {sSegBufH,sSegBufL} | out | 1,1 | {0,sda,scl} | 0 |
2 | miniCPUでI2Cバスを操作(手動クロック供給) | {0,1,0} | BCx | BNx | {8{0},data} | {sSegBufH,sSegBufL} | {data,out[7:0]} | out[1],out[0] | {0,sda,scl} | 0 |
3 | miniCPU自動クロック供給のときのクロック分周値設定 | {0,1,1} | BCx | 0 | {8{0},data} | {{0},cpuCs,abus,dbus} | {data,out[7:0]} | out[1],out[0] | {0,sda,scl} | 0 |
4 | miniCPUの独立実行(自動クロック供給) | {1,0,0} | dclk | ssRun(自動スタート) | swx | {sSegBufH,sSegBufL} | out | 1,1 | {0,sda,scl} | BCx |
5 | miniCPUでI2Cバスを操作(自動クロック供給) | {1,0,1} | dclk | ssRun(自動スタート) | {8{0},data} | sSegBufH,sSegBufL} | {data,out[7:0]} | out[1],out[0] | {0,sda,scl} | BCx |
module top(sSegAnode, sSegCathode, sw, ledOut, colorLed_1, colorLed_2, bu, bd, bl, br, bc, scl, sda, jc, bclck ); output [7:0] sSegAnode; output [7:0] sSegCathode; output [15:0] ledOut; // led[8] ... if sda is sending, corresponding to the last sended sda, else corresponding to the last received sda // it is shifted to left when a positive edge of scl is detected. // led[0] corresponding to sw[0] // led[1] corresponding to sw[1] // led[2] corresponsing to center button, bc. output [2:0] colorLed_1; output [2:0] colorLed_2; // color LED output [3:0] jc; input [15:0] sw; // sw[15:8] ... for setting sda send data, sw[7:0] ... for controlling // sw[0] ... if 1 scl is not ready, else scl is ready; // sw[1] ... if 1 sda is receiving(1), else sda is sending(0). // sw[2] ... sending sda. input bu, bd, bl, br, bc, bclck; // bd corresponding to !reset. // bc corresponding to scl. scl=sw[0]|bc // if posedge bl is detected, sw is shown in hex in the 7seg led array. inout scl, sda; reg sclx, sdax; reg [3:0] jcx; assign scl=(~sclx)?1'b0:1'bz; assign sda=(~sdax)?1'b0:1'bz; assign jc=jcx; wire BNx, BWx, BEx, BCx; // reset: BSx // BWx, BEx ... change operationMode // wire [15:0] swx; wire reset; // reg sclRw, sdaRw; // write=1, read=0; wire cpuClk; wire cpuRun; reg [7:0] data; reg [2:0] operationMode; // operationMode: 0 ... manual operation of peripherals // 1 ... CPU independent // 2 ... CPU, I2C connected reg [15:0] ledWire,cpuIn; wire [2:0] cpuCs; wire [11:0] pcout,abus; wire [15:0] irout,qtop,dbus,out; reg [31:0] sSegArray; reg [15:0] led; wire start; wire haltIn; wire halt; wire [15:0] sSegBufL; wire [15:0] sSegBufH; reg [4:0] divide; wire dclk; initial begin divide={01101}; end assign ledOut=led; reg [2:0] colorLed_1x; wire [2:0] colorLed_2x; // assign colorLed_1=colorLed_1x; assign colorLed_2=colorLed_2x; assign reset=~bd; always @(posedge sclx, negedge reset) begin if(!reset) begin data<=0; end else data<={data[6:0],sda}; end // for operation mode always @(posedge BEx or negedge reset ) begin if(!reset) begin operationMode<=3'b000; end else case (operationMode) 3'b000: operationMode<=3'b001; 3'b001: operationMode<=3'b010; 3'b010: operationMode<=3'b011; 3'b011: operationMode<=3'b100; 3'b100: operationMode<=3'b101; 3'b101: operationMode<=3'b110; 3'b110: operationMode<=3'b000; default operationMode<=3'b000; endcase end /* always @(posedge BWx or negedge reset ) begin if(!reset) begin operationMode<=0; end else case (operationMode) 3'b000: operationMode<=3'b110; 3'b001: operationMode<=3'b000; 3'b010: operationMode<=3'b001; 3'b011: operationMode<=3'b010; 3'b100: operationMode<=3'b011; 3'b101: operationMode<=3'b100; 3'b110: operationMode<=3'b101; default operationMode<=3'b000; endcase end */ /* */ // assign setDivide=(operationMode==3'b011)?BCx:1'b0; always @(posedge BCx ) begin if(operationMode==3'b011) begin divide<=swx[15:11]; end end assign colorLed_2x={dclk,scl,sda}; assign start=(operationMode==3'b100|operationMode==3'b101)?BCx:1'b0; assign cpuClk=(operationMode==3'b100|operationMode==3'b101)? dclk:BCx; assign cpuRun=(operationMode==3'b100|operationMode==3'b101)? ssRun:BNx; assign haltIn=(operationMode==3'b100|operationMode==3'b101)? halt:1'b0; assign sSegBufL=BWx?irout:out; assign sSegBufH=BWx?{{0},cpuCs,abus}:pcout; // always @(operationMode or swx[0] or BCx or data or BNx or cpuCs or out or sda or scl or out[0] or out[1]) begin // always @(posedge BEx or posedge BWx or negedge reset) begin always @(operationMode) begin case(operationMode) 3'b000: begin // direct i2c operation only colorLed_1x=3'b000; cpuIn=0; sSegArray={{16{0}},data,swx[7:0]}; led[15:8]=data; led[7:0]=swx[7:0]; sclx=BCx; sdax=swx[0]; jcx=swx[5:2]; end 3'b001: begin // mini CPU, with manual clock only ... for start ... push BTN, keep, push BTC, release BTN, BTC colorLed_1x=3'b001; // blue cpuIn=swx; sSegArray={sSegBufH,sSegBufL}; led=out; sclx=1'b1; sdax=1'b1; jcx={0,0,0,0}; end 3'b010: begin // mini CPU, with manual clock, with i2c IO colorLed_1x=3'b010; //green cpuIn={swx[15:8],data}; sSegArray={sSegBufH, sSegBufL}; led[15:8]=data; led[7:0]=out[7:0]; sclx=out[1]; sdax=out[0]; jcx=out[5:2]; end 3'b011: begin // set clock divider for mini CPU with automatic clock colorLed_1x=3'b011; // cyan .. aqua cpuIn=0; sSegArray={divide,{13{0}},data,swx[7:0]}; led[15:8]=divide; led[7:0]=swx[7:0]; sclx=1; sdax=1; jcx={0,0,0,0}; end 3'b100: begin // mini CPU, only, with automatic clock, colorLed_1x=3'b100; // red cpuIn=swx; sSegArray={sSegBufH, sSegBufL}; led=out; sclx=1'b1; sdax=1'b1; jcx={0,0,0,0}; end 3'b101: begin // mini CPU, with automatic clock, with i2c IO colorLed_1x=3'b101; // purple cpuIn={swx[15:8],data}; sSegArray={sSegBufH, sSegBufL}; led[15:8]=data; led[7:0]=out[7:0]; sclx=out[1]; sdax=out[0]; jcx=out[5:2]; end default begin colorLed_1x=3'b000; cpuIn=swx; sSegArray={{0{16}},data,swx[7:0]}; led[15:8]=data; led[7:0]=swx[7:0]; sclx=BCx; sdax=swx[0]; jcx=swx[5:2]; end endcase end chattering #(20) chattering0(.clk(bclck), .reset(reset), .in({bu,bl,br,bc,sw}), .out({BNx, BWx, BEx, BCx,swx})); /* for test bench assign BNx=bu; assign BWx=bl; assign BEx=br; assign BCx=bc; assign swx=sw; */ sSegArray sSegArray0(.clk(bclck), .reset(reset), .load(1'b1), .d(sSegArray), .anode(sSegAnode), .cathode(sSegCathode)); minicpu minicpu0(.clk(cpuClk), .reset(reset), .run(cpuRun), .in(cpuIn), .cs(cpuCs), .pcout(pcout), .irout(irout), .qtop(qtop), .abus(abus), .dbus(dbus), .out(out), .haltx(haltIn)); clockDivider clockDivider0(.clk(bclck),.reset(reset), .div(divide), .dclk(dclk)); cpuStartStopSequence cpuStartStopSequence0(.clk(dclk), .reset(reset), .start(start), .run(ssRun), .halt(halt)); endmodule
## This file is a general .ucf for the Nexys4 rev B board ## To use it in a project: ## - uncomment the lines corresponding to used pins ## - rename the used signals according to the project ## Clock signal NET "bclck" LOC = "E3" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L12P_T1_MRCC_35, Sch name = CLK100MHZ #NET "clk" TNM_NET = sys_clk_pin; #TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100 MHz HIGH 50%; ## Switches NET "sw<0>" LOC = "U9" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L21P_T3_DQS_34, Sch name = SW0 NET "sw<1>" LOC = "U8" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_25_34, Sch name = SW1 NET "sw<2>" LOC = "R7" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L23P_T3_34, Sch name = SW2 NET "sw<3>" LOC = "R6" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L19P_T3_34, Sch name = SW3 NET "sw<4>" LOC = "R5" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L19N_T3_VREF_34, Sch name = SW4 NET "sw<5>" LOC = "V7" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L20P_T3_34, Sch name = SW5 NET "sw<6>" LOC = "V6" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L20N_T3_34, Sch name = SW6 NET "sw<7>" LOC = "V5" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L10P_T1_34, Sch name = SW7 NET "sw<8>" LOC = "U4" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L8P_T1-34, Sch name = SW8 NET "sw<9>" LOC = "V2" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L9N_T1_DQS_34, Sch name = SW9 NET "sw<10>" LOC = "U2" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L9P_T1_DQS_34, Sch name = SW10 NET "sw<11>" LOC = "T3" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L11N_T1_MRCC_34, Sch name = SW11 NET "sw<12>" LOC = "T1" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L17N_T2_34, Sch name = SW12 NET "sw<13>" LOC = "R3" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L11P_T1_SRCC_34, Sch name = SW13 NET "sw<14>" LOC = "P3" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L14N_T2_SRCC_34, Sch name = SW14 NET "sw<15>" LOC = "P4" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L14P_T2_SRCC_34, Sch name = SW15 ## LEDs NET "ledOut<0>" LOC = "T8" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L24N_T3_34, Sch name = LED0 NET "ledOut<1>" LOC = "V9" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L21N_T3_DQS_34, Sch name = LED1 NET "ledOut<2>" LOC = "R8" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L24P_T3_34, Sch name = LED2 NET "ledOut<3>" LOC = "T6" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L23N_T3_34, Sch name = LED3 NET "ledOut<4>" LOC = "T5" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L12P_T1_MRCC_34, Sch name = LED4 NET "ledOut<5>" LOC = "T4" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L12N_T1_MRCC_34, Sch name = LED5 NET "ledOut<6>" LOC = "U7" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L22P_T3_34, Sch name = LED6 NET "ledOut<7>" LOC = "U6" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L22N_T3_34, Sch name = LED7 NET "ledOut<8>" LOC = "V4" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L10N_T1_34, Sch name = LED8 NET "ledOut<9>" LOC = "U3" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L8N_T1_34, Sch name = LED9 NET "ledOut<10>" LOC = "V1" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L7N_T1_34, Sch name = LED10 NET "ledOut<11>" LOC = "R1" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L17P_T2_34, Sch name = LED11 NET "ledOut<12>" LOC = "P5" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L13N_T2_MRCC_34, Sch name = LED12 NET "ledOut<13>" LOC = "U1" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L7P_T1_34, Sch name = LED13 NET "ledOut<14>" LOC = "R2" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L15N_T2_DQS_34, Sch name = LED14 NET "ledOut<15>" LOC = "P2" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L15P_T2_DQS_34, Sch name = LED15 NET "colorLed_1<2>" LOC = "K5" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L5P_T0_34, Sch name = LED16_R NET "colorLed_1<1>" LOC = "F13" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L5P_T0_AD9P_15, Sch name = LED16_G NET "colorLed_1<0>" LOC = "F6" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L19N_T3_VREF_35, Sch name = LED16_B NET "colorLed_2<2>" LOC = "K6" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_0_34, Sch name = LED17_R NET "colorLed_2<1>" LOC = "H6" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_24P_T3_35, Sch name = LED17_G NET "colorLed_2<0>" LOC = "L16" | IOSTANDARD = "LVCMOS33"; #Bank = CONFIG, Pin name = IO_L3N_T0_DQS_EMCCLK_14, Sch name = LED17_B ## 7 segment display NET "sSegCathode<7>" LOC = "L3" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L2N_T0_34, Sch name = CA NET "sSegCathode<6>" LOC = "N1" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L3N_T0_DQS_34, Sch name = CB NET "sSegCathode<5>" LOC = "L5" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L6N_T0_VREF_34, Sch name = CC NET "sSegCathode<4>" LOC = "L4" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L5N_T0_34, Sch name = CD NET "sSegCathode<3>" LOC = "K3" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L2P_T0_34, Sch name = CE NET "sSegCathode<2>" LOC = "M2" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L4N_T0_34, Sch name = CF NET "sSegCathode<1>" LOC = "L6" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L6P_T0_34, Sch name = CG NET "sSegCathode<0>" LOC = "M4" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L16P_T2_34, Sch name = DP NET "sSegAnode<0>" LOC = "N6" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L18N_T2_34, Sch name = AN0 NET "sSegAnode<1>" LOC = "M6" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L18P_T2_34, Sch name = AN1 NET "sSegAnode<2>" LOC = "M3" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L4P_T0_34, Sch name = AN2 NET "sSegAnode<3>" LOC = "N5" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L13_T2_MRCC_34, Sch name = AN3 NET "sSegAnode<4>" LOC = "N2" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L3P_T0_DQS_34, Sch name = AN4 NET "sSegAnode<5>" LOC = "N4" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L16N_T2_34, Sch name = AN5 NET "sSegAnode<6>" LOC = "L1" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L1P_T0_34, Sch name = AN6 NET "sSegAnode<7>" LOC = "M1" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L1N_T034, Sch name = AN7 ## Buttons #NET "btnCpuReset" LOC = "C12" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L3P_T0_DQS_AD1P_15, Sch name = CPU_RESET NET "bc" LOC = "E16" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L11N_T1_SRCC_15, Sch name = BTNC NET "bu" LOC = "F15" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L14P_T2_SRCC_15, Sch name = BTNU NET "bl" LOC = "T16" | IOSTANDARD = "LVCMOS33"; #Bank = CONFIG, Pin name = IO_L15N_T2_DQS_DOUT_CSO_B_14, Sch name = BTNL NET "br" LOC = "R10" | IOSTANDARD = "LVCMOS33"; #Bank = 14, Pin name = IO_25_14, Sch name = BTNR NET "bd" LOC = "V10" | IOSTANDARD = "LVCMOS33"; #Bank = 14, Pin name = IO_L21P_T3_DQS_14, Sch name = BTND ## Pmod Header JC #NET "JC<0>" LOC = "K2" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L23P_T3_35, Sch name = JC1 #NET "JC<1>" LOC = "E7" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L6P_T0_35, Sch name = JC2 #NET "JC<2>" LOC = "J3" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L22P_T3_35, Sch name = JC3 #NET "JC<3>" LOC = "J4" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L21P_T3_DQS_35, Sch name = JC4 #NET "JC<4>" LOC = "K1" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L23N_T3_35, Sch name = JC7 #NET "JC<5>" LOC = "E6" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L5P_T0_AD13P_35, Sch name = JC8 #NET "JC<6>" LOC = "J2" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L22N_T3_35, Sch name = JC9 #NET "JC<7>" LOC = "G6" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L19P_T3_35, Sch name = JC10 NET "jc<0>" LOC = "K1" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L23N_T3_35, Sch name = JC7 NET "jc<1>" LOC = "E6" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L5P_T0_AD13P_35, Sch name = JC8 NET "jc<2>" LOC = "J2" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L22N_T3_35, Sch name = JC9 NET "jc<3>" LOC = "G6" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L19P_T3_35, Sch name = JC10 ## Temperature Sensor #NET "tmpSCL" LOC = "F16" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L14N_T2_SRCC_15, Sch name = TMP_SCL #NET "tmpSDA" LOC = "G16" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L13N_T2_MRCC_15, Sch name = TMP_SDA #NET "tmpInt" LOC = "D14" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L1P_T0_AD0P_15, Sch name = TMP_INT #NET "tmpCT" LOC = "C14" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L1N_T0_AD0N_15, Sch name = TMP_CT #NET "scl" LOC = "F16" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L14N_T2_SRCC_15, Sch name = TMP_SCL #NET "sda" LOC = "G16" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L13N_T2_MRCC_15, Sch name = TMP_SDA #NET "tmpInt" LOC = "D14" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L1P_T0_AD0P_15, Sch name = TMP_INT #NET "tmpCT" LOC = "C14" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L1N_T0_AD0N_15, Sch name = TMP_CT NET "scl" LOC = "F16" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L14N_T2_SRCC_15, Sch name = TMP_SCL NET "sda" LOC = "G16" | IOSTANDARD = "LVCMOS33"; #Bank = 15, Pin name = IO_L13N_T2_MRCC_15, Sch name = TMP_SDA
module chattering(clk, reset, in, out ); parameter N=1; input clk, reset; input [N-1:0]in; output [N-1:0]out; reg [N-1:0]out; reg [21:0] count; always @(posedge clk or negedge reset) if(!reset) count <=0; else count <= count +1; always @(posedge clk) if(count==0) out <= in; endmodule
module sSegArray( clk,reset,load,d, anode, cathode ); parameter N=32; input clk,reset,load; input [N-1:0] d; output [7:0] anode; output [7:0] cathode; reg [7:0] anode; reg [7:0] cathode; reg [31:0] q; wire [2:0] selectedSeg; wire [7:0] wOneSeg; reg segClk; counter #(8) waitOneSeg(.clk(clk), .reset(reset), .load(1'b0), .inc(1'b1), .d(16'h0000), .q(wOneSeg)); //assign segClk= (wOneSeg==0)? ~segClk: segClk; always @(posedge clk, negedge reset) begin if(!reset) segClk<=0; else if (wOneSeg==0) segClk<=~segClk; end counter #(3) selector(.clk(segClk),.reset(reset),.load(1'b0), .inc(1'b1), .d(4'h0), .q(selectedSeg)); //counter #(3) selector(.clk(clk), .reset(reset), .load(0), .inc(1), .d(4'h0), .q(selectedSeg)); always @(posedge clk, negedge reset) begin if(!reset) anode=8'hFE; // note! anode is connected by pnp transistor. else // in order to active one 7seg, low should be setted to the 7seg. case (selectedSeg) 3'b000: anode=8'hFE; 3'b001: anode=8'hFD; 3'b010: anode=8'hFB; 3'b011: anode=8'hF7; 3'b100: anode=8'hEF; 3'b101: anode=8'hDF; 3'b110: anode=8'hBF; 3'b111: anode=8'h7F; endcase end reg [3:0] selectedVal; always @(posedge clk, negedge reset) begin if(!reset) cathode=8'h03; // note! when one segment of the cathode is low, else // and its anode is low, the segment glow. case (selectedVal) // ca 4'b0000: cathode=8'h03; //8'hfc; 0 ------ 4'b0001: cathode=8'h9f; //8'h60; 1 / / 4'b0010: cathode=8'h25; //8'hda; 2 /cf / cb 4'b0011: cathode=8'h0d; //8'hf2; 3 / / 4'b0100: cathode=8'h99; //8'h66; 4 ----- 4'b0101: cathode=8'h49; //8'hb6; 5 / cg / 4'b0110: cathode=8'h41; //8'hbe; 6 /ce / cc 4'b0111: cathode=8'h1f; //8'he0; 7 / / 4'b1000: cathode=8'h01; //8'hfe; 8 ------ . ch 4'b1001: cathode=8'h09; //8'hf6; 9 cd 4'b1010: cathode=8'h11; //8'hee; A 4'b1011: cathode=8'hc1; //8'h3e; B 4'b1100: cathode=8'h63; //8'h9c; C 4'b1101: cathode=8'h85; //8'h7c; D 4'b1110: cathode=8'h61; //8'h9e; E 4'b1111: cathode=8'h71; //8'h8e; F endcase end always @(posedge clk, negedge reset) begin if(!reset) selectedVal=q[3:0]; else case (selectedSeg) 3'b000: selectedVal=q[3:0]; 3'b001: selectedVal=q[7:4]; 3'b010: selectedVal=q[11:8]; 3'b011: selectedVal=q[15:12]; 3'b100: selectedVal=q[19:16]; 3'b101: selectedVal=q[23:20]; 3'b110: selectedVal=q[27:24]; 3'b111: selectedVal=q[31:28]; endcase end always @(posedge clk, negedge reset) begin if(!reset) q=0; else if(load) q=d; end endmodule
module clockDivider(clk, reset, div, dclk); input clk, reset; input [4:0] div; output dclk; reg dclk; reg [31:0] q; always @(posedge clk or negedge reset) begin if(!reset) q <=0; else q<=q+1; end always @(posedge clk) begin dclk<=q[div]; end endmodule
module cpuStartStopSequence(clk, reset, start, run, halt ); input clk, reset, start; reg [3:0] cs; output run; reg run; output halt; reg halt; always @(posedge clk or negedge reset) if(!reset) begin cs<= 4'b0000; run<=1'b0; halt<=1'b0; end else case(cs) 4'b0000: if(start) begin cs <= 4'b0001; end 4'b0001: if(!start) begin cs <= 4'b0010; run <= 1; end 4'b0010: cs <= 4'b0011; 4'b0011: begin cs <= 4'b0100; run <=0; end 4'b0100: if(start ) begin cs <= 4'b0101; end 4'b0101: begin cs <= 4'b0110; halt <=1'b1; end 4'b0110: cs <= 4'b0111; 4'b0111: cs <= 4'b1000; 4'b1000: cs <= 4'b1001; 4'b1001: begin cs <= 4'b0000; halt <=1'b0; end default: cs <= 3'bxxx; endcase endmodule