![[PukiWiki]](image/pukiwiki.png "[PukiWiki]")
| operationMode | Color LED 1 | cpuClk | cpuRun | cpuIn | sSegArray? | led | sclx, sdax | Color LED 2 |
| 0 | {0,0,0} | 0 | 0 | 0 | {16{0}, data,swx[7:0]} | {data,swx[7:0]} | BCx,swx[0] | {0,sda,scl} |
| 1 | {0,0,1} | BCx | BNx | swx | {{0},cpuCs,pcout,irout} | out | 1,1 | {0,sda,scl} |
| 2 | {0,1,0} | BCx | BNx | {8{0},data} | {{0},cpuCs,abus,dbus} | {data,out[7:0]} | out[1],out[0] | {0,sda,scl} |
module top(sSegAnode, sSegCathode, sw, ledOut, colorLed_1, colorLed_2,
bu, bd, bl, br, bc, scl, sda,
bclck
);
output [7:0] sSegAnode;
output [7:0] sSegCathode;
output [15:0] ledOut; // led[8] ... if sda is sending, corresponding to the last sended sda,
// else corresponding to the last received sda
// it is shifted to left when a positive edge of scl is detected.
// led[0] corresponding to sw[0]
// led[1] corresponding to sw[1]
// led[2] corresponsing to center button, bc.
output [2:0] colorLed_1;
output [2:0] colorLed_2; // color LED
input [15:0] sw; // sw[15:8] ... for setting sda send data, sw[7:0] ... for controlling
// sw[0] ... if 1 scl is not ready, else scl is ready;
// sw[1] ... if 1 sda is receiving(1), else sda is sending(0).
// sw[2] ... sending sda.
input bu, bd, bl, br, bc, bclck; // bd corresponding to !reset.
// bc corresponding to scl. scl=sw[0]|bc
// if posedge bl is detected, sw is shown in hex in the 7seg led array.
inout scl, sda;
reg sclx, sdax;
assign scl=(~sclx)?1'b0:1'bz;
assign sda=(~sdax)?1'b0:1'bz;
wire BNx, BWx, BEx, BCx;
// reset: BSx
// BWx, BEx ... change operationMode
//
wire [15:0] swx;
wire reset;
// reg sclRw, sdaRw; // write=1, read=0;
reg cpuClk,cpuRun;
reg [7:0] data;
reg [1:0] operationMode;
// operationMode: 0 ... manual operation of peripherals
// 1 ... CPU independent
// 2 ... CPU, I2C connected
reg [15:0] ledWire,cpuIn;
wire [2:0] cpuCs;
wire [11:0] pcout,abus;
wire [15:0] irout,qtop,dbus,out;
reg [31:0] sSegArray;
reg [15:0] led;
assign ledOut=led;
reg [2:0] colorLed_1x, colorLed_2x;
//
assign colorLed_1=colorLed_1x;
// assign colorLed_2=colorLed_2x;
assign reset=~bd;
// always @(sclx or sdax ) begin
// colorLed_2x[0]<=sclx;
// colorLed_2x[1]<=sdax;
// colorLed_2x[2]<=0;
// end
assign colorLed_2={0,sda,scl};
always @(posedge sclx, negedge reset) begin
if(!reset) begin
data<=0;
end
else
data<={data[6:0],sda};
end
// for operation mode
always @(posedge BEx or negedge reset) begin
if(!reset) begin
operationMode<=0;
end
else
if(BEx) operationMode<=operationMode+1;
end
// always @(operationMode or swx[0] or BCx or data or BNx or cpuCs or out or sda or scl or out[0] or out[1]) begin
always @(operationMode) begin
case(operationMode)
0: begin
colorLed_1x=3'b000;
cpuClk=0; cpuRun=0; cpuIn=0;
sSegArray={{16{0}},data,swx[7:0]};
led[15:8]=data;
led[7:0]=swx[7:0];
sclx=BCx;
sdax=swx[0];
end
1: begin // CPU independent,
colorLed_1x=3'b001;
cpuClk=BCx; cpuRun=BNx; cpuIn=swx;
sSegArray={{0},cpuCs,pcout,irout};
led={{0{16}},out};
sclx=1'b1;
sdax=1'b1;
end
2: begin
colorLed_1x=3'b010;
cpuClk=BCx; cpuRun=BNx; cpuIn={{8{0}},data};
sSegArray={{0},cpuCs,abus,dbus};
led[15:8]=data;
led[7:0]=out[7:0];
sclx=out[1];
sdax=out[0];
end
default begin
colorLed_1x=3'b011;
cpuClk=BCx; cpuRun=BNx; cpuIn=swx;
sSegArray={{0{16}},data,swx[7:0]};
led[15:8]=data;
led[7:0]=swx[7:0];
sclx=BCx;
sdax=swx[0];
end
endcase
end
chattering #(20) chattering0(.clk(bclck), .reset(reset), .in({bu,bl,br,bc,sw}), .out({BNx, BWx, BEx, BCx,swx}));
// assign BNx=bu;
// assign BWx=bl;
// assign BEx=br;
// assign BCx=bc;
// assign swx=sw;
sSegArray sSegArray0(.clk(bclck), .reset(reset), .load(1), .d(sSegArray), .anode(sSegAnode), .cathode(sSegCathode));
minicpu minicpu0(.clk(cpuClk), .reset(reset), .run(cpuRun), .in(cpuIn), .cs(cpuCs), .pcout(pcout), .irout(irout), .qtop(qtop), .abus(abus), .dbus(dbus), .out(out));
endmodulemodule ram(clk, load, addr, d, q ); parameter DWIDTH=16, AWIDTH=12, WORDS=4096; input clk, load; input [AWIDTH-1:0] addr; input [DWIDTH-1:0] d; output [DWIDTH-1:0] q; reg [DWIDTH-1:0] q; reg [DWIDTH-1:0] mem [WORDS-1:0]; always @(posedge clk) begin if(load) mem[addr] <= d; q <= mem[addr]; end integer i; initial begin for(i=0; i<WORDS; i=i+1) mem[i]=12'h000; mem[8'h00] = 16'h1000; // PUSHI 0 mem[8'h01] = 16'h3011; // POP i ... i=0; mem[8'h02] = 16'h2011; // L1 PUSH i mem[8'h03] = 16'h1012; // PUSHI C mem[8'h04] = 16'hF000; // ADD mem[8'h05] = 16'h7000; // LD ... C[i]; mem[8'h06] = 16'hE000; // OUT ... print(C[i]) ; mem[8'h07] = 16'h2011; // PUSH i; mem[8'h08] = 16'h1001; // PUSH 1 mem[8'h09] = 16'hF000; // ADD mem[8'h0A] = 16'h3011; // POP i mem[8'h0B] = 16'h2011; // PUSH i mem[8'h0C] = 16'h2010; // PUSH n mem[8'h0D] = 16'hF001; // SUB mem[8'h0E] = 16'h6002; // JNZ L1: if(i<n) goto L1; mem[8'h0F] = 16'h0000; // L2: HALT mem[8'h10] = 16'h0076; // n: 0x76 ... 0x88-0x12 mem[8'h11] = 16'h0000; // i: // // data for controlling i2c // (MSB) ...... scl, sda (LSB) mem[8'h12] = 16'h0003; // C: 11 mem[8'h13] = 16'h0002; // 10 start mem[8'h14] = 16'h0000; // 00 mem[8'h15] = 16'h0001; // 01 mem[8'h16] = 16'h0003; // 11 sda 1 mem[8'h17] = 16'h0001; // 01 mem[8'h18] = 16'h0000; // 00 mem[8'h19] = 16'h0002; // 10 sda 10 mem[8'h1A] = 16'h0000; // 00 mem[8'h1B] = 16'h0002; // 10 sda 100 mem[8'h1C] = 16'h0000; // 00 mem[8'h1D] = 16'h0001; // 01 mem[8'h1E] = 16'h0003; // 11 sda 1001 mem[8'h1F] = 16'h0001; // 01 mem[8'h20] = 16'h0000; // 00 mem[8'h21] = 16'h0002; // 10 sda 10010 mem[8'h22] = 16'h0000; // 00 mem[8'h23] = 16'h0001; // 01 mem[8'h24] = 16'h0003; // 11 sda 100101 mem[8'h25] = 16'h0001; // 01 mem[8'h26] = 16'h0003; // 11 sda 1001011 .. 0x4B mem[8'h27] = 16'h0001; // 01 mem[8'h28] = 16'h0000; // 00 mem[8'h29] = 16'h0002; // 10 send 0 ... write mem[8'h2A] = 16'h0000; // 00 mem[8'h2B] = 16'h0001; // 01 mem[8'h2C] = 16'h0003; // 11 read ack mem[8'h2D] = 16'h0001; // 01 mem[8'h2E] = 16'h0000; // 00 mem[8'h2F] = 16'h0002; // 10 write 0 mem[8'h30] = 16'h0000; // 00 mem[8'h31] = 16'h0002; // 10 write 00 mem[8'h32] = 16'h0000; // 00 mem[8'h33] = 16'h0002; // 10 write 000 mem[8'h34] = 16'h0000; // 00 mem[8'h35] = 16'h0002; // 10 write 0000 mem[8'h36] = 16'h0000; // 00 mem[8'h37] = 16'h0002; // 10 write 00000 mem[8'h38] = 16'h0000; // 00 mem[8'h39] = 16'h0002; // 10 write 000000 mem[8'h3A] = 16'h0000; // 00 mem[8'h3B] = 16'h0002; // 10 write 0000000 mem[8'h3C] = 16'h0000; // 00 mem[8'h3D] = 16'h0002; // 10 write 00000000 .... write register 0 mem[8'h3E] = 16'h0000; // 00 mem[8'h3F] = 16'h0001; // 01 mem[8'h40] = 16'h0003; // 11 read ack mem[8'h41] = 16'h0001; // 01 mem[8'h42] = 16'h0003; // 11 mem[8'h43] = 16'h0002; // 10 ... repeat start mem[8'h44] = 16'h0000; // 00 mem[8'h45] = 16'h0001; // 01 mem[8'h46] = 16'h0003; // 11 sda 1 mem[8'h47] = 16'h0001; // 01 mem[8'h48] = 16'h0000; // 00 mem[8'h49] = 16'h0002; // 10 sda 10 mem[8'h4A] = 16'h0000; // 00 mem[8'h4B] = 16'h0002; // 10 sda 100 mem[8'h4C] = 16'h0000; // 00 mem[8'h4D] = 16'h0001; // 01 mem[8'h4E] = 16'h0003; // 11 sda 1001 mem[8'h4F] = 16'h0001; // 01 mem[8'h50] = 16'h0000; // 00 mem[8'h51] = 16'h0002; // 10 sda 10010 mem[8'h52] = 16'h0000; // 00 mem[8'h53] = 16'h0001; // 01 mem[8'h54] = 16'h0003; // 11 sda 100101 mem[8'h55] = 16'h0001; // 01 mem[8'h56] = 16'h0003; // 11 sda 1001011 .. 0x4B mem[8'h57] = 16'h0001; // 01 mem[8'h58] = 16'h0003; // 11 send 1 ... read mem[8'h59] = 16'h0001; // 01 mem[8'h5A] = 16'h0003; // 11 read ack mem[8'h5B] = 16'h0001; // 01 mem[8'h5C] = 16'h0003; // 11 read 1st bit mem[8'h5D] = 16'h0001; // 01 mem[8'h5E] = 16'h0003; // 11 read 2nd bit mem[8'h5F] = 16'h0001; // 01 mem[8'h60] = 16'h0003; // 11 read 3rd bit mem[8'h61] = 16'h0001; // 01 mem[8'h62] = 16'h0003; // 11 read 4th bit mem[8'h63] = 16'h0001; // 01 mem[8'h64] = 16'h0003; // 11 read 5th bit mem[8'h65] = 16'h0001; // 01 mem[8'h66] = 16'h0003; // 11 read 6th bit mem[8'h67] = 16'h0001; // 01 mem[8'h68] = 16'h0003; // 11 read 7th bit mem[8'h69] = 16'h0001; // 01 mem[8'h6A] = 16'h0003; // 11 read 8th bit mem[8'h6B] = 16'h0001; // 01 mem[8'h6C] = 16'h0000; // 00 mem[8'h6D] = 16'h0002; // 10 write ack mem[8'h6E] = 16'h0000; // 00 mem[8'h6F] = 16'h0001; // 01 mem[8'h70] = 16'h0003; // 11 read ack mem[8'h71] = 16'h0001; // 01 mem[8'h72] = 16'h0003; // 11 read 1st bit mem[8'h73] = 16'h0001; // 01 mem[8'h74] = 16'h0003; // 11 read 2nd bit mem[8'h75] = 16'h0001; // 01 mem[8'h76] = 16'h0003; // 11 read 3rd bit mem[8'h77] = 16'h0001; // 01 mem[8'h78] = 16'h0003; // 11 read 4th bit mem[8'h79] = 16'h0001; // 01 mem[8'h7A] = 16'h0003; // 11 read 5th bit mem[8'h7B] = 16'h0001; // 01 mem[8'h7C] = 16'h0003; // 11 read 6th bit mem[8'h7D] = 16'h0001; // 01 mem[8'h7E] = 16'h0003; // 11 read 7th bit mem[8'h7F] = 16'h0001; // 01 mem[8'h80] = 16'h0003; // 11 read 8th bit mem[8'h81] = 16'h0001; // 01 mem[8'h82] = 16'h0003; // 11 write NACK mem[8'h83] = 16'h0001; // 01 mem[8'h84] = 16'h0000; // 00 mem[8'h85] = 16'h0002; // 10 mem[8'h86] = 16'h0003; // 11 stop the transfering mem[8'h87] = 16'h0001; // 01 end endmodule
