top.v
module top(sSegAnode, sSegCathode, sw, bu, bd, bl, br, bc, bclck
);
output [7:0] sSegAnode;
output [7:0] sSegCathode;
input [15:0] sw;
input bu, bd, bl, br, bc, bclck;
wire BNx, BWx, BEx, BCx;
wire reset;
assign reset=~bd;
chattering #(4) chattering0(.clk(bclck), .reset(reset), .in({bu,bl,br,bc}), .out({BNx, BWx, BEx, BCx}));
// assign BNx=BN;
// assign BWx=BW;
// assign BEx=BE;
// assign BCx=BC;
sSegArray sSegArray0(.clk(bclck), .reset(reset), .load(BWx), .d({{16{0}},sw}), .anode(sSegAnode), .cathode(sSegCathode));
endmodule